Wafer Level Testing: An Introduction
Wafer level tests are used to test device design and process performance. Wafer tests provide many devices or test structures to obtain a statistically important number of test results to assess device design and production processes. These tests have become more important since new materials, device designs and new production processes often do not have far-reaching pre-production testing to establish device performance, device reliability, device lifetime, process development and new materials integration into production. Semiautomatic analytical test stations are usually used to use test engineering time efficiently.
Objectives of Wafer Test Scheduling
The main focus of wafer test scheduling is to reduce production cost and increase output while meeting delivery dates. The functional test operations are the last stage of the semiconductor fabrication process before the wafers leave the manufacturing facility. The outputs of the test processes are finished devices that are usually either custom-built or made-to-stock. In the make-to-order environment, on-time delivery is important to ensure customer service. For instance, in the Application Specific Integrated Circuit (ASIC) market, the circuits on the wafer devices are custom designed for customers with specific due date requirement. Hence, reducing the number of slow jobs or minimizing maximum slowness is often used as the criteria for scheduling in the custom-built environment. On the contrary, in the make-to-stock environment, maximizing output is a more common objective. Throughput is the number of finished lots in a certain time horizon. For instance, in the DRAM market, the devices are standard products that are produced in high volume and a specific due date is often not related with each wafer device. In this case, a major importance is placed on high output and equipment utilization, while decreasing the mean and the variance of cycle times (Reha et al, 47-58)..................
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